Currently, a Cortex-A9 Multi-Processor core (MPcore) is put forward by ARM, a leading semiconductor intellectual attribute supplier. The Cortex-A9 MPcore supports up to four processors. Memory coherency is ensured between processors in a cluster through a Snooping Control Unit (SCU). A cluster includes four processors.
Generally, a Level-1 (L1) cache exists in a cluster. To further improve efficiency of reading data, a Level-2 (L2) cache is generally configured for the cluster. However, the L1 cache of the Cortex-A9 MPcore supports write-back only, and does not support write-through, namely, cannot update the L2 cache synchronously after updating the L1 cache, which leads to cache incoherency between clusters.
The ARM Cortex-A9 series currently provide no solution to collaboration between more than four processors, which makes it rather inconvenient to apply more than four processors. For example, a product requires architecture that includes more than four processors. A task needs to be distributed into multiple processors and processed in pipeline mode. If a task is processed by one cluster but is terminated by another cluster, the pipeline processing needs to be performed between different clusters, which causes cache incoherency between clusters.